1. Field of the Invention
The present invention relates to a multilayer capacitor that not only can realize both downsizing and higher capacity, but also is excellent in thermal stress resistance even when a large number of layers of internal electrodes are stacked, and more particularly, to that suitable for use as a multilayer ceramic chip capacitor.
2. Description of the Related Art
A multilayer capacitor such as a multilayer ceramic chip capacitor having a sandwich structure in which dielectric layers made of ceramic and internal electrodes are stacked has been conventionally known. As a device on which such a multilayer capacitor is to be mounted is becoming more downsized and coming to have a higher performance, further downsizing of the multilayer capacitor and further increase in its capacitance are rapidly underway in recent years. In order to realize both downsizing and higher capacity of the multilayer capacitor, it is basically necessary to reduce the thickness per layer of the dielectric layers to make a further multilayered structure.
Meanwhile, margin portions formed only of dielectrics exist on upper, lower, right, and left sides of a portion formed of a stack of dielectric layers and internal electrodes in a multilayer body being a main body of the multilayer capacitor. Conventionally, however, the size of the margin portions has not been specifically stipulated, and the margin portions have dimensions to a degree not causing a lowered yield in a manufacturing process of the multilayer capacitors.
Note that in manufacturing the multilayer capacitor, the right and left margin portions on right and left sides of the internal electrodes have been generally formed to have a relatively wider dimension than the dimension of the upper and lower margin portions on upper and lower sides of the internal electrodes. The upper and lower margin portions and right and left margin portions in which no internal electrode exists tend to be reduced in size in accordance with the recent trend toward thinner and more multilayered dielectric layers accompanying the aforesaid downsizing of the multilayer capacitor and increase in its capacity.
However, heat for soldering or the like is given to the multilayer body when the multilayer capacitor is mounted on a substrate, so that thermal stress occurs in this multilayer body, and with the reduction in size of the margin portions due to the increase in the number of stacked layers, a tendency of a weakened resistance of the multilayer body against this thermal stress has come to be observed.